The Peripheral Component Interconnect (PCI) specification (downloadable from www.pci-sig com) defines how one or more peripheral devices can communicate with a computing device over a serial input/output bus link. The serial link can be within a single computing device or can link one or more computing devices and peripheral devices. The original PCI specification defines a 32-bit PCI bus that operates at 33 MHz with a peak throughput of 132 Megabytes/second. Until recently, the performance of the original PCI specification was adequate for most applications. As the processing rates of commercially available processors have increased, the processing capacity of the processors to process data eventually exceeded the capacity of the PCI bus to deliver data. Thus, recent piocessors can process data faster than the PCI bus can deliver the data to processor.
An updated version of the PCI specification, referred to as PCI Express, proposes to improve the computer performance by increasing the flow of data between a processor and various peripheral devices, such as network cards, printers and storage disks. Rather than transmitting data on a parallel bus, which limits the maximum transmitting speed, PCI-Express uses high speed serial lanes at 2.5 Gbit/second or higher to transmit the data. When multiple lanes are used, e.g., 32 lanes, the maximum speed can be up to 80 Gbit/second.
In addition, PCI-Express includes a number of new features that are said to improve reliability, timing and scalability of the bus. For example, the PCI-Express standard requires that transmitters support a “receiver detect” function that allows a transmitter to determine whether there is a receiver present at the far end of a communication link. A need therefore exists for a receiver detection circuit that may be employed by a transmitter that communicates over a PCI-Express bus.